This invention relates to a memory system and, in particular, to a memory system in which "new" bits of information can be written into a memory array and from which "old" (i.e., previously written) bits of information can be read out at the same time, without interference between the read and the write functions.
A need exists for a memory system (also referred to as a "path" memory) having a memory array into which a stream of data bits can be written into sequential locations, at great speed. However, the data being loaded into the memory may not be absolutely accurate due to some form of transmission noise. To handle the problem associated with the receipt and storage of inaccurate data, a Viterbi algorithm was developed. After a number of data bits have been written in sequence into the memory, as in 20/20 hindsight, the algorithm "replays" the received data in reverse sequence (e.g., backwards) to see if the chosen state change at each time step was optimum. Thus, for example, after information has been sequentially written and stored in 2N locations of a path memory at a predetermined data rate, the data stored in the memory must be read out, in reverse order, from these 2N locations at twice the data rate. At the same time another N locations must be filled with incoming data at the normal data rate since it is assumed that data is being continuously received. As each new group of N data bits are received and stored in N bit locations (path points), the path memory stores the "new" group of data bits while also enabling the previous 2N data bits (points) to be reviewed in reverse order to the order in which they were received and stored.
A prior art memory system configured to perform the function of accepting "new" data and concurrently reading out, in reverse order, previously received data is shown in block diagram form in FIG. 1. In FIG. 1, the memory system is implemented with three individual memories or memory blocks (MEM 1, MEM 2, MEM 3). Each one of the memory blocks MEM 1, MEM 2 and MEM 3 is coupled to an input data bus, 7, and to an output data bus, 8, and each memory has its own address decoder, 9a, 9b, and 9c.
The function of writing information into the memory system and concurrently reading information from the system is implemented using three memory blocks because the address order and data sample rates are different in the Read and Write cycles. Each memory block is used in a different manner during each of three overall "PHASES". During any one of the three PHASES, one of the three memories is in a Write mode while the other two memories are in a Read-out mode. At the end of each PHASE the read or write function of the memory blocks changes.
For example, in a first PHASE (PHASE 1), Memory 1 is written with N path identifiers at a frequency of Fs in address ascending order while Memory 3 and then Memory 2 are read out at a frequency of 2 Fs in descending order starting at the top of Memory 3. Subsequently, the phase increments to a second phase (PHASE 2) where the incoming data is written into Memory 2 in ascending order while Memory 1 and Memory 3 are read in descending order starting at the top of Memory 1. After that, in the third phase (PHASE 3), Memory 3 is written in ascending order while Memory 2 and Memory 1 are read in descending order starting at the top of MEMORY 2. The memories are then repeatedly cycled through the sequence just outlined.
A sequence of writing and reading the memory system, in accordance with the prior art would be essentially as outlined below:
PHASE I--Write MEM1 and Read Out MEM3 and then Read Out MEM2; PA0 PHASE II--Write MEM2 and Read out MEM1 and then MEM3; and PA0 PHASE III--Write MEM3 and Read MEM2 and then MEM1.
Evidently, the prior art memory structure requires considerable logic for switching the memories, sequencing the memory addresses in both directions (count up and down) and switching addressing rates between read and write modes.
An object of the present invention is to produce the required read-write memory function using a simpler and more integrated structure.